QuadriSparse: RISC-V Sparse Matrix Accelerator

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I am currently writing my master's thesis with the goal of designing a hardware accelerator for sparse matrix multiplication and integrating it with a RISC-V core. The accelerator will be deployed on a FPGA for testing and validation.

QuadriSparse is a sparse dense matrix mulitplication (SpMM) accelerator and RISC-V ISA extention based on the matrix multiplication co-processor Quadrilatero. It uses the CORE-V-X-IF interface to interface with OpenHW Group CPUs and the OBI protocol to interface with memories.

We have achieved 2-8x performnace improvements compared to its dense counterpart for maticies with high levels of sparsity.

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