Master Thesis
QuadriSparse: RISC-V Sparse Matrix Accelerator and ISA Extension
Sparse dense matrix multiplication (SpMM) is an important operation in many applications such as inference and training of pruned large language models, graph analytics and scientific computing. Most accelerators only support sparse operations which limit their usefulness in cases where the result is reused as the SpMM operation naturally produces results with greater density than its sparse operand.
This thesis explores the prospect of extending an accelerator for dense matrix multiplication to support SpMM to find out how efficient SpMM accelerator is at very small scales.
We introduce QuadriSparse, an SpMM extension to the small and efficient RISC-V accelerator Quadrilatero, designed for unstructured sparsity. The accelerator includes three new instructions to load a tile of the sparse matrix SPLD, load a tile of the dense matrix DLD, and multiply the two using Gustavson's algorithm SPMAC.
QuadriSparse improves the execution time by up to 6.6x at 99% sparsity compared to dense operations on Quadrilatero and begins to outperform the baseline at 95%. This was achieved with an area overhead of 4.6% in LUTs and 23% in DSP-blocks in FPGA synthesis
